Structure and method for low resistance interconnections

Details Structure and method for low resistance interconnections Structure and method for low resistance interconnections

2007-03-29

2010-06-15

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S624000, C438S638000, C438S622000, C257S752000, C257S251000, C257S751000, C257S622000

Reexamination Certificate

active

07737026

ABSTRACT:
A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.

REFERENCES:
patent: 6028362 (2000-02-01), Omura
patent: 6157081 (2000-12-01), Nariman et al.
patent: 6562715 (2003-05-01), Chen
patent: 2003/0194858 (2003-10-01), Lee
patent: 2004/0209456 (2004-10-01), Farrar
patent: 2005/0250314 (2005-11-01), Park
patent: 2006/0097397 (2006-05-01), Russell
patent: 2006/0240187 (2006-10-01), Weidman

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