Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2008-07-15
2010-12-28
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S154000, C438S155000, C438S158000, C438S162000, C438S166000, C257SE21414
Reexamination Certificate
active
07858455
ABSTRACT:
A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for a channel formation region, the microcrystalline semiconductor layer is formed of a stacked layer of a microcrystalline semiconductor film which is formed by a deposition method and can be a nucleus of crystal growth and an amorphous semiconductor film; a conductive film and a semiconductor film which forms a source region and a drain region and to which an impurity imparting one conductivity is added are formed over the amorphous semiconductor film; and the conductive film is irradiated with laser light. The amorphous semiconductor film over the microcrystalline semiconductor film is crystallized by the laser light, and the microcrystalline semiconductor layer including the microcrystalline semiconductor film formed by a deposition method can be formed.
REFERENCES:
patent: 4619034 (1986-10-01), Janning
patent: 5028551 (1991-07-01), Dohjo et al.
patent: 5198379 (1993-03-01), Adan
patent: 5294811 (1994-03-01), Aoyama et al.
patent: 5453858 (1995-09-01), Yamazaki
patent: 5591987 (1997-01-01), Yamazaki et al.
patent: 5701167 (1997-12-01), Yamazaki
patent: 5834345 (1998-11-01), Shimizu
patent: 5849601 (1998-12-01), Yamazaki
patent: 6023075 (2000-02-01), Yamazaki
patent: 6218702 (2001-04-01), Yamazaki et al.
patent: 6242758 (2001-06-01), Yamazaki et al.
patent: 6252249 (2001-06-01), Yamazaki
patent: 6268235 (2001-07-01), Sakakura et al.
patent: 6287888 (2001-09-01), Sakakura et al.
patent: 6306213 (2001-10-01), Yamazaki
patent: 6797548 (2004-09-01), Zhang et al.
patent: 6838324 (2005-01-01), Yamazaki et al.
patent: 6979840 (2005-12-01), Yamazaki et al.
patent: 7067844 (2006-06-01), Yamazaki
patent: 7098479 (2006-08-01), Yamazaki
patent: 7115902 (2006-10-01), Yamazaki
patent: 2005/0012097 (2005-01-01), Yamazaki
patent: 2007/0018165 (2007-01-01), Yamazaki
patent: 04-242724 (1992-08-01), None
Lee et al., “High-Mobility Nanocrystalline Silicon Thin-Film Transistors Fabricated by Plasma-Enhanced Chemical Vapor Deposition”, Appl. Phys. Lett. (Applied Physics Letters ), May 24, 2005, vol. 86, pp. 222106-1-222106-3.
Lee et al., “High Mobility N-Channel and P-Channel Nanocrystalline Silicon Thin-Film Transistors”, IEEE, 2005, pp. 937-940.
Lee et al., “Directly Deposited Nanocrystalline Silicon Thin-Film Transistors with Ultra High Mobilities”, Appl. Phys. Lett. (Applied Physics Letters ), Dec. 18, 2006, vol. 89, pp. 252101-1-252101-3.
Lee et al., “How to Achieve High Mobility Thin Film Transistors by Direct Deposition of Silicon Using 13.56 MHz RF PECVD?”, IEDM, 2006, pp. 295-298.
Esmaeili et al., “High Stability, Low Leakage Nanocrystalline Silicon Bottom Gate Thin Film Transistors for AMOLED Displays”, IEEE, 2006, pp. 303-306.
Lee et al., “Leakage Current Mechanisms in Top-Gate Nanocrystalline Silicon Thin-Film Transistors”, Appl. Phys. Lett. (Applied Physics Letters ), Feb. 28, 2008, vol. 92, pp. 083509-1-083509-3.
Esmaeili et al., “Absence of Defect State Creation in Nanocrystalline Silicon Thin-Film Transistors Deduced from Constant Current Stress Measurements”, Appl. Phys. Lett. (Applied Physics Letters ), Sep. 12, 2007, vol. 91, pp. 113511-1-113511-3.
Lee et al., “Stability of nc-Si:H TFTs Wth Silicon Nitride Gate Dielectric”, IEEE Transactions on Electron Devices, 2007, vol. 54, No. 1, pp. 45-51.
Sazonov et al., “Low-Temperature Materials and Thin Film Transistors for Flexible Electronics”, Proceedings of the IEEE, Aug. 1, 2005, vol. 93, No. 8, pp. 1420-1428.
Esmaeili et al., “Stability of Nanocrystalline Silicon Bottom-Gate Thin-Film Transistors with Silicon Nitride Gate Dielectrics”, J. Appl. Phys. (Journal of Applied Physics ), Sep. 28, 2007, vol. 102, pp. 064512-1- 064512-7.
Lee et al., “Top-Gate TFTs Using 13.56MHz PECVD Microcrystalline Silicon”, IEEE Electron Device Letters, Sep. 5, 2005, vol. 26, No. 9, pp. 637-639.
Lee et al., “Postdeposition Thermal Annealing and Material Stability of 75° C. Hydrogenated Nanocrystalline Silicon Plasma-Enhanced Chemical Vapor Deposition Films”, J. Appl. Phys. (Journal of Applied Physics ), Aug. 4, 2005, vol. 98, pp. 034305-1-034305-7.
Arai et al., “Micro Silicon Technology for Active Matrix OLED Display”, SID '07 Digest, May 23-25, 2007, pp. 1370-1373.
Duong Khanh B
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Smith Zandra
LandOfFree
Method for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4150798