Thin film transistor array panel and manufacturing method...

Details Thin film transistor array panel and manufacturing method... Thin film transistor array panel and manufacturing method...

2007-03-01

2009-12-15

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C257SE21320

Reexamination Certificate

active

07632723

ABSTRACT:
Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form data lines and drain electrodes. A photoresist is formed, and the upper film is patterned using the photoresist as an etch mask to expose contact portions of the lower film of the drain electrodes. Exposed portions of the extrinsic a-Si layer and the intrinsic a-Si layer are removed, and then the photoresist and underlying portions of the extrinsic a-Si layer are removed. A passivation layer is formed and patterned along with the gate insulating layer to form contact holes exposing the contact portions of the lower film, and pixel electrodes are formed to contact the contact portions.

REFERENCES:
patent: 5986738 (1999-11-01), Tagusa et al.
patent: 6087678 (2000-07-01), Kim
patent: 6407780 (2002-06-01), Sung
patent: 6545293 (2003-04-01), Wong
patent: 6713786 (2004-03-01), Colgan et al.
patent: 7205570 (2007-04-01), Kim et al.
patent: 2002/0053701 (2002-05-01), Kong et al.
patent: 2002/0140895 (2002-10-01), Kimura et al.
patent: 2007/0138474 (2007-06-01), Kim et al.
patent: 1020000038604 (2000-07-01), None
patent: 1020000040967 (2000-07-01), None
patent: 20020037845 (2002-05-01), None
patent: 1020020083249 (2002-11-01), None
patent: 1020030094606 (2003-12-01), None

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