Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

Filed on

2007-06-29

Date issued

2009-06-09

Examiner

Dinh, Son (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Signals

Other Related Categories

C365S201000, C365S222000, C365S194000, C365S189070

Type

Reexamination Certificate

Status

active

Patent number

07545687

Description

ABSTRACT:
A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS timing test signal. The RAS timing controller generates a RAS timing signal. The bank controller controls a refresh operation timing in response to an output of the input buffer in a test mode and the RAS timing signal in a normal mode.

REFERENCES:
patent: 5793685 (1998-08-01), Suma
patent: 5825705 (1998-10-01), Tsukude et al.
patent: 1999-009107 (1999-02-01), None
patent: 10-0218733 (1999-06-01), None
patent: 2003-0001826 (2003-01-01), None
patent: 10-2004-0093789 (2004-11-01), None

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