DRAM including a tunable gain amp as a local sense amp

Details DRAM including a tunable gain amp as a local sense amp DRAM including a tunable gain amp as a local sense amp

2009-04-19

2009-12-01

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189140, C365S194000, C365S203000, C365S229000

Reexamination Certificate

active

07626848

ABSTRACT:
DRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a capacitor, and gain of the tunable gain amp is adjusted by setting a local amp voltage for reading the memory cell more effectively with optimized gain. And a global sense amp is connected to the local sense amp for receiving a read output. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as a reference signal. In addition, alternative circuits are described.

REFERENCES:
patent: 5715189 (1998-02-01), Asakura
patent: 6426905 (2002-07-01), Dennard et al.
patent: 6456521 (2002-09-01), Hsu et al.
patent: 2009/0190415 (2009-07-01), Kim
A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM in VLSI Circuits, Digest of Technical Papers, May 1993.
A 322 MHz Random-Cycle Embedded DRAM With High-Accuracy Sensing and Tuning, IEEE Journal of Solid-State Circuits, vol. 40, No. 11, Nov. 2005.
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier, IEEE International Solid-State Circuits Conference, pp. 486, 2007.

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