Frozen ring cache

Details Frozen ring cache Frozen ring cache

2006-12-13

2009-12-01

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C713S001000, C711S129000

Reexamination Certificate

active

07627718

ABSTRACT:
A processor having multiple cores and a multiple cache segments, each core associated with one of the cache segments, the cache segments interconnected by a data communication ring, and logic to disallow operation of the ring at a startup event and to execute an initialization sequence at one or more of the cores so that each of the one or more of the cores operates using the cache segment associated with the core as a read-write memory during the initialization sequence

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Eswaramoorthi, Nallusamy, “A Framework for Using Processor Cache as RAM (CAR)”, Coreboot Documentation (slides), Oct. 10, 2005, XP002518963, University of Mexico, URL: http://wvvw.coreboot.org/images/6/6c/LBCar.pdf., whole document.

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