Memory usable in cache mode or scratch pad mode to reduce...

Details Memory usable in cache mode or scratch pad mode to reduce... Memory usable in cache mode or scratch pad mode to reduce...

2005-07-25

2009-06-09

Thai, Tuan V. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S100000, C711S118000, C711S154000

Reexamination Certificate

active

07546437

ABSTRACT:
A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises a first portion and a second portion, and only one of the portions is active at a time. The non-active portion is unusable to store or retrieve data (e.g., Java local variables). When the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.

REFERENCES:
patent: 6604168 (2003-08-01), Ogawa
patent: 6772310 (2004-08-01), Thompson et al.
patent: 6915307 (2005-07-01), Mattis et al.
patent: 6988167 (2006-01-01), Allen et al.
patent: 7032158 (2006-04-01), Alvarez et al.
patent: 7065613 (2006-06-01), Flake et al.
patent: 7200721 (2007-04-01), Lang et al.

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