Semiconductor memory device and manufacturing method therefor

Details Semiconductor memory device and manufacturing method therefor Semiconductor memory device and manufacturing method therefor

2007-06-08

2009-12-08

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S354000

Reexamination Certificate

active

07629651

ABSTRACT:
This disclosure concerns a semiconductor memory comprising Fin-type semiconductor layers (Fins) provided on the insulation layer provided on a substrate; first gate insulation films provided on first side surfaces of the Fins; second gate insulation films provided on second side surfaces of the Fins, the second side surfaces being opposite sides of the first side surfaces of the Fins; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fins and a second side surface of the other Fin which is adjacent to the one of the Fins, the second side surface of the one of the Fins is opposed to the second side surface of the other Fin, wherein widths of the front gate electrodes or the back gate electrodes are smaller than the feature size (F).

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T. Tanaka, et al., “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM”, IEDM Tech. Dig., 2004, 4 Pages.
Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.

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