Semiconductor scheme for reduced circuit area in a...

Details Semiconductor scheme for reduced circuit area in a... Semiconductor scheme for reduced circuit area in a...

2007-10-22

2009-12-01

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S327000, C438S197000

Reexamination Certificate

active

07626220

ABSTRACT:
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

REFERENCES:
patent: 4983544 (1991-01-01), Lu et al.
patent: 5124280 (1992-06-01), Wei et al.
patent: 5536683 (1996-07-01), Lin et al.
patent: 5699282 (1997-12-01), Allen et al.
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6313510 (2001-11-01), Sung-Bong et al.
patent: 6468899 (2002-10-01), Choi
patent: 6593217 (2003-07-01), Fujisawa
patent: 6864136 (2005-03-01), Brown et al.

Affiliated with

Also associated with

Rating

Semiconductor scheme for reduced circuit area in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor scheme for reduced circuit area in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor scheme for reduced circuit area in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4144097