Circuit for and a method of generating an interleaver address

Details Circuit for and a method of generating an interleaver address Circuit for and a method of generating an interleaver address

2006-01-17

2009-06-30

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

Reexamination Certificate

active

07555684

ABSTRACT:
A method of generating interleaver addresses in a circuit for decoding data is disclosed. The method comprises the steps of receiving a data stream having a plurality of data blocks, each block having N bits; dividing each data block of the plurality of data blocks into m windows, each window comprising N/m bits; and calculating an interleaver address for each window as a function of modulo N/m. A circuit for generating an interleaver address in a circuit for decoding data is also disclosed.

REFERENCES:
patent: 6775800 (2004-08-01), Edmonston et al.
patent: 6910110 (2005-06-01), Kim et al.
patent: 7058874 (2006-06-01), Zhou

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