Semiconductor device

Details Semiconductor device Semiconductor device

2008-06-05

2009-11-17

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S034000, C326S087000

Reexamination Certificate

active

07619439

ABSTRACT:
When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.

REFERENCES:
patent: 6947336 (2005-09-01), Kim et al.
patent: 7084663 (2006-08-01), Oguri
patent: 2006/0158198 (2006-07-01), Fujisawa
patent: 2007/0194798 (2007-08-01), Fujisawa
patent: 2007/0263459 (2007-11-01), Kim et al.
patent: 2005-167779 (2005-06-01), None
patent: 2006-203405 (2006-08-01), None

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