Semiconductor device and dram integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S306000

Reexamination Certificate

active

07495275

ABSTRACT:
A semiconductor device with a multi-layer wiring structure includes a first conductive region: a second conductive region that has an upper surface located in a higher position than the first conductive region with respect to the substrate; an insulating that covers the first and second conductive regions; a wiring groove that is formed in the insulating film so as to expose the second conductive region; a contact hole that is formed in the insulating film so as to expose the first conductive region; and a wiring pattern that fills the wiring groove and the contact hole. In this semiconductor device, the upper surface of the wiring pattern is located on the same plane as the upper surface of the insulating film.

REFERENCES:
patent: 6259149 (2001-07-01), Burkhardt et al.
patent: 6433381 (2002-08-01), Mizutani et al.
patent: 2002/0014648 (2002-02-01), Fujitsu
patent: 2002/0153548 (2002-10-01), Fujitsu
patent: 2002/0179955 (2002-12-01), Morimoto et al.
patent: 5-152449 (1993-06-01), None
patent: 10-200075 (1998-07-01), None
patent: 11-214650 (1999-08-01), None
patent: 2000-77407 (2000-03-01), None
patent: 2002-50748 (2002-02-01), None

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