Semiconductor device having separated drain regions

Details Semiconductor device having separated drain regions Semiconductor device having separated drain regions

2006-08-15

2009-12-29

Dickey, Thomas L (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C365S049110

Reexamination Certificate

active

07638849

ABSTRACT:
A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region formed between the first and second drain regions; and a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region.

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P. Mongkolkachit et al., “Design Technique for Mitigation of Alpha-Particle-Induced Single-Event Transients in Combinational Logic,” IEEE Transactions on Device and Material Reliability, vol. 3:3, Sep. 2003, pp. 89-92.
N. Seifert, et al., “Frequency Dependence of Soft Error Rates for Sub-Micron CMOS Technologies,” IEDM Technical Digest, pp. 323-326, (2001).

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