Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-07-31
2009-06-30
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S129000, C711S154000, C711S156000, C711S173000
Reexamination Certificate
active
07555611
ABSTRACT:
A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to store two groups of local variables. A first group comprises local variables associated with finished methods and a second group comprises local variables associated with unfinished methods. Further, local variables are saved to, or fetched from, external memory upon a context change based on a threshold value differentiating the first and second groups. The first value may comprise a threshold address or an allocation bit associated with each of a plurality of lines forming the data memory.
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Chauvel Gerard
Kuusela Maija
Lasserre Serge
Brady III Wade James
Bragdon Reginald G
Gu Shawn X
Neerings Ronald O.
Telecky , Jr. Frederick J.
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