Shift register and semiconductor display device

Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop

Reexamination Certificate

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Details

C327S241000

Reexamination Certificate

active

07602215

ABSTRACT:
The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

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