Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-04
2009-10-27
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S125000, C712S237000
Reexamination Certificate
active
07610449
ABSTRACT:
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.
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Davis Gordon T.
Doing Richard W.
Jabusch John D.
Krishna M V V Anil
Olsson Brett
Cockburn Joscelyn G.
Farrokh Hashem
International Business Machines - Corporation
McBurney Mark E.
McConnell Daniel E.
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