Optimization of SMI handling and initialization

Details Optimization of SMI handling and initialization Optimization of SMI handling and initialization

2003-10-06

2009-02-17

Auve, Glenn A (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S269000

Reexamination Certificate

active

07493435

ABSTRACT:
A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

REFERENCES:
patent: 5530891 (1996-06-01), Gephardt
patent: 5613071 (1997-03-01), Rankin et al.
patent: 5761516 (1998-06-01), Rostoker et al.
patent: 5768585 (1998-06-01), Tetrick et al.
patent: 5938765 (1999-08-01), Dove et al.
patent: 5978903 (1999-11-01), Quimby et al.
patent: 5996058 (1999-11-01), Song et al.
patent: 6065121 (2000-05-01), Hobson et al.
patent: 6158000 (2000-12-01), Collins
patent: 6192442 (2001-02-01), Haren et al.
patent: 6237120 (2001-05-01), Shimada et al.
patent: 6272618 (2001-08-01), Tyner et al.
patent: 6282601 (2001-08-01), Goodman et al.
patent: 6308278 (2001-10-01), Khouli et al.
patent: 6374338 (2002-04-01), Garvey
patent: 6446213 (2002-09-01), Yamaki
patent: 6611911 (2003-08-01), O'Shea et al.
patent: 6615329 (2003-09-01), Scott et al.
patent: 6711642 (2004-03-01), Huang
patent: 6775734 (2004-08-01), Chang
patent: 6782472 (2004-08-01), Jain et al.
patent: 6792480 (2004-09-01), Chaiken et al.
patent: 6836849 (2004-12-01), Brock et al.
patent: 6842857 (2005-01-01), Lee et al.
patent: 6848046 (2005-01-01), Zimmer
patent: 6925556 (2005-08-01), Hill et al.
patent: 6968410 (2005-11-01), Bennett et al.
patent: 6968412 (2005-11-01), Nalawadi
patent: 7043729 (2006-05-01), Lewis
patent: 7146515 (2006-12-01), Harrington et al.
patent: 7152169 (2006-12-01), Cooper et al.
patent: 2002/0099893 (2002-07-01), Nguyen et al.
patent: 2003/0009654 (2003-01-01), Nalawadi et al.
patent: 2003/0093579 (2003-05-01), Zimmer et al.
patent: 2003/0224768 (2003-12-01), Adjamah
patent: 2004/0034854 (2004-02-01), Cottrell
patent: 0 720 094 (1996-07-01), None
patent: 0 817 038 (1998-01-01), None
patent: 0 818 736 (1998-01-01), None
patent: 2 382 180 (2003-05-01), None
Kobayashi, et al. U.S. Appl. No. 10/307,146, Filed Nov. 30, 2002, “Apparatus and Method for Multi-Threaded Processors Performance Control,” 36 pages.

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