Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-08-04
2009-08-18
Smith, Bradley K (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE21210
Reexamination Certificate
active
07576386
ABSTRACT:
A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.
REFERENCES:
patent: 4173766 (1979-11-01), Hayes
patent: 4630086 (1986-12-01), Sato et al.
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6026026 (2000-02-01), Chan et al.
patent: 6074917 (2000-06-01), Chang et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6218700 (2001-04-01), Papadas
patent: 6512696 (2003-01-01), Fan et al.
patent: 6624028 (2003-09-01), Wen
patent: 6680509 (2004-01-01), Wu et al.
patent: 6709928 (2004-03-01), Jenne et al.
patent: 6720630 (2004-04-01), Mandelman et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6818558 (2004-11-01), Rathor et al.
patent: 6897533 (2005-05-01), Yang et al.
patent: 6912163 (2005-06-01), Zheng et al.
patent: 6977201 (2005-12-01), Jung
patent: 7115942 (2006-10-01), Wang
patent: 2003/0030100 (2003-02-01), Lee et al.
patent: 2003/0047755 (2003-03-01), Lee et al.
patent: 2003/0089935 (2003-05-01), Fan et al.
patent: 2003/0146465 (2003-08-01), Wu
patent: 2003/0224564 (2003-12-01), Kang et al.
patent: 2004/0079983 (2004-04-01), Chae et al.
patent: 2004/0152260 (2004-08-01), Rabkin et al.
patent: 2004/0183126 (2004-09-01), Bae et al.
patent: 2005/0006696 (2005-01-01), Noguchi et al.
patent: 2005/0074937 (2005-04-01), Jung
patent: 2005/0101089 (2005-05-01), Kim et al.
patent: 2006/0258090 (2006-11-01), Bhattacharyya et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 1411555 (2006-11-01), None
patent: 2004 363329 (2004-12-01), None
Chindalore, G.L., et al., A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories, IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003 Silicon Devices, pp. 257-259.
Eitan, B., et al., NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell, IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Ito, F., et al., A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 80-81.
Minami, S., et al., New Scaling Guidelines for MNOS Nonvolatile Memory Devices, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991, pp. 2519-2526.
Sung, S.K., et al., Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time, IEEE 2002 Silicon Nanoelectronics Workshop, (Honolulu HI, USA) Jun. 9-10, 2002 p. 83-84.
Walker, A.J., 3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications, 2003 Symposium on VLSI Technology Digest of Technical Papers, 2 pages (unnumbered).
White, M.H., et al. On the Go with SONOS, IEEE, Circuits & Devices, Jul. 2000, pp. 22-31.
Cho et al., “Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells,” IEEE Electron Dev. Lett. 24(4) Apr. 2003 260-267.
Shih et al., “A Novel 2-bit/cell Nitride Storage Flash Memory with Greater than 1M P/E-cycle Endurance,” IEEE IEDM 04-881-884, 2004, 36.31-36.3.4.
Blomme et al., “Multilayer tunneling barriers for nonvolatile memory applicatins,” Device Research Conference 2002, 60th DRC Conf. Digest 153-154.
Blomme et al., “Write/Erase Cycling Endurance of Memory Cells with Si02/Hfo2 Tunnel Dielectric,” IEEE Trans. on Device and Materials Reliability 4(3), Sep. 2004, 345-351.
Govoreanu et al., “VARIOT. A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Device Letters 24(2), Feb. 2003, 99-101.
Govoreanu et al. “Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003, 299-302.
Govoreanu et al., “An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions,” IEEE SISPAD Intl. Conf., Sep. 3-5 2003, 287-290.
Kim et al., “Robust Multi-bit Programmable Flash Memory Using a Resonant Tunnel Barrier,” Electron Devices Mtg., Dec. 5-7, 2005, IEDM Tech Digest, 861-864.
Likharev, “Layered tunnel barriers for nonvolatile memory devices,” Appl. Phys. Lett. 73(15) Oct. 1998, 2137-2139.
Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” IEDM Tech. Digest, Dec. 2005, 547-550.
Aminzadeh, et al, “Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxode-Silicon Structures under Positive Gate Bias,” IEEE Transactions on Electron Devices 35(4) Apr. 1998, 459-467.
Yamada, et al., “A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM,” Proc. of IEDM IEEE Dec. 1991 307-310.
Takata, M., et al., “New Non-Volatile Memory with Extremely High Density Metal Nano-Dots,” IEEE IEDM 03-553, 22.5.1-22.5.4.
Lee, Chungho, et al., “Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals,” IEEE IEDM.03-557, 22.6.1-22.6.4.
Baik, Seung, et al., “High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier,” IEEE IEDM 03-545 22.3.1-22.3.4.
Lee, Chang, et al., “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-Giga Bit Flash Memeries,” IEEE 2003 4 pages.
Notice of Allowance mailed Aug. 28, 2008, U.S. Appl. No. 11/554,455, 12 pages.
Office Action mailed May 30, 2008 in U.S. Appl. No. 11/300,813, 22 pages.
Office Action Mailed Sep. 17, 2008 in U.S. Appl. No. 11/324,492, 9 pages.
Response to Sep. 17, 2008 Office Action filed on Dec 15, 2008 in U.S. Appl. No. 11/324,492, 7 pages.
Supplemental Amendment filed on Dec. 29, 2008 in U.S. Appl. No. 11/324,492, 36 pages.
Office Action Mailed Sep. 17, 2008 in U.S. Appl. No. 11/324,492, 9 pages.
Lai Erh-Kun
Lue Hang-Ting
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Movva Amar
Smith Bradley K
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