Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-21
2009-02-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07496876
ABSTRACT:
One aspect of the present invention includes a method for generating functional testcases for multiple boolean algorithms from a single generic testcase template. In one embodiment, the method includes the preliminary step of creating a generic testcase template containing user-entered mask levels shapes and grouping the shapes within each mask level of the template. Next, testcase generation code comprising mask build language is developed to copy and rename the mask levels from the template into the desired input levels necessary to test a mask build operation. Finally, testcase generation code is executed to generate a testcase. The testcase generation code can be easily modified as necessary to change the mask levels. Additionally, shape interactions for new mask level builds can be added into the generic testcase template, allowing the template to be reused to generate additional testcases.
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Hirning Robert M.
International Business Machines - Corporation
Oppenheimer Wolff & Donnelly LLP
Siek Vuthe
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