Memory checking device and method for checking a memory

Details Memory checking device and method for checking a memory Memory checking device and method for checking a memory

2006-04-06

2009-11-17

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S736000

Reexamination Certificate

active

07620884

ABSTRACT:
A memory checking device for cells arranged in memory rows and columns, wherein, in a state of integrity, the memory has parity values for two memory rows or two columns that differ from each other with the same parity value calculation rule or with different parity value calculation rules or are equal with different parity value calculation rules. The checking device includes a reader for reading out the binary memory values of the two memory columns or rows. The memory checking device includes a checking unit designed to calculate the parity value according to the calculation rule valid for the corresponding memory column or row for the two memory columns or the two rows, and to compare it with an expected parity value for the state of integrity, and, in the case of a deviation, to provide an error indication in one of the rows or one of the columns.

REFERENCES:
patent: 4103823 (1978-08-01), Aichelmann, Jr. et al.
patent: 5862158 (1999-01-01), Baylor et al.
patent: 6871317 (2005-03-01), Corbett
patent: 2004/0117723 (2004-06-01), Foss
patent: 2007/0214403 (2007-09-01), Longwell et al.

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