Method of manufacturing an integrated circuit

Details Method of manufacturing an integrated circuit Method of manufacturing an integrated circuit

Filed on

2007-06-04

Date issued

2009-08-25

Examiner

Richards, N Drew (Department: 2895)

Patent Class

Semiconductor device manufacturing: process

SubClass

Coating with electrically or thermally conductive material

SubSubClass

To form ohmic contact to semiconductive material

Other Related Categories

C438S118000, C438S406000, C438S455000, C257SE21122, C257SE21088, C257SE21526

Type

Reexamination Certificate

Status

active

Patent number

07579268

Description

ABSTRACT:
A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.

REFERENCES:
patent: 4235648 (1980-11-01), Richardson
patent: 5193014 (1993-03-01), Takenouchi et al.
patent: 5492863 (1996-02-01), Higgins, III
patent: 6372624 (2002-04-01), Farnworth et al.
patent: 6492255 (2002-12-01), Enomoto et al.
patent: 6503343 (2003-01-01), Tench et al.
patent: 6664874 (2003-12-01), Shirasaki
patent: 6696347 (2004-02-01), Hikita et al.
patent: 6817073 (2004-11-01), Uchiyama et al.
patent: 6900117 (2005-05-01), Yoda
patent: 6905915 (2005-06-01), Yuzawa
patent: 7148608 (2006-12-01), Baumgartner et al.
patent: 2001/0020546 (2001-09-01), Eldridge et al.
patent: 2001/0036711 (2001-11-01), Urushima
patent: 2001/0040290 (2001-11-01), Sakurai et al.
patent: 2002/0117330 (2002-08-01), Eldridge et al.
patent: 2003/0219926 (2003-11-01), Yuzawa
patent: 2004/0132230 (2004-07-01), Kim
patent: 2006/0126313 (2006-06-01), Steiner et al.
patent: 2006/0292750 (2006-12-01), James et al.
patent: 2001358173 (2001-12-01), None
patent: 01/20676 (2001-03-01), None
patent: 2005/064668 (2005-07-01), None

Affiliated with

Also associated with

Rating

Method of manufacturing an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4126620