Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-01-23
2009-11-17
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S131000, C712S031000
Reexamination Certificate
active
07620780
ABSTRACT:
Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled to the parent processor, and a dual port memory is respectively associated with each child processor part and parcel of a unified memory architecture. The parent processor may then dynamically distribute sub-cache components to dual-port memories based upon a scatter-gather work unit decomposition pattern. A parent cache controller reads, in response to a memory request from a child processor and an address translation pattern from the parent processor, a set of data from non-contiguous addresses of the data cache according to the address translation pattern, and writes the set of data to contiguous addresses of the dual port memory associated with the requesting child processor.
REFERENCES:
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Anderson, James B., “Direct Memory Access-Based Multi-Processor Array”, filed Aug. 30, 2006, pp. 1-27, U.S. Appl. No. 11/513,575, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Bailey, David H., “A High-Performance FFT Algorithm for Vector Supercomputers”, Nov. 23, 1987, pp. 1-9, vol. 2, No. 1, International Journal of Supercomputer Applictions, available from NASA Ames Research Center, Moffett Field, CA 94035.
Bailey, David H., “Unfavorable Strides in Cache Memory Systems”, Dec. 9, 1994, pp. 1-10, vol. 4, Scientific Programming, available from NASA Ames Research Center, Moffett Field, CA 94035.
Farrokh Hashem
Maunu LeRoy D.
Peugh Brian R
XILINX Inc.
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