Semiconductor chips having redistributed power/ground lines...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead

Reexamination Certificate

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C257S758000, C257S781000

Reexamination Certificate

active

07545037

ABSTRACT:
Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

REFERENCES:
patent: 5774340 (1998-06-01), Chang et al.
patent: 6008543 (1999-12-01), Iwabuchi
patent: 6211576 (2001-04-01), Shimizu et al.
patent: 6235552 (2001-05-01), Kwon et al.
patent: 6590295 (2003-07-01), Liao et al.
patent: 7096581 (2006-08-01), Thomas et al.
patent: 10-261663 (1998-09-01), None
patent: 2003-0006915 (2003-01-01), None
patent: 2004-0006744 (2004-01-01), None
English language abstract of Korean Publication No. 2003-0006915.
English language abstract of Korean Publication No. 2004-0006744.
English language abstract of Japanese Publication No. 10-261663.

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