Method and apparatus for masking known fails during memory...

Details Method and apparatus for masking known fails during memory... Method and apparatus for masking known fails during memory...

2006-04-04

2009-02-10

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S719000

Reexamination Certificate

active

07490274

ABSTRACT:
Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

REFERENCES:
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patent: 5729551 (1998-03-01), Park et al.
patent: 6735727 (2004-05-01), Lee
patent: 6920072 (2005-07-01), Theel
patent: 2001/0044916 (2001-11-01), Blodgett

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