Substrate coupled noise isolation for integrated circuits

Details Substrate coupled noise isolation for integrated circuits Substrate coupled noise isolation for integrated circuits

2004-05-05

2009-06-02

Wojciechowicz, Edward (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S373000, C257S401000, C257S500000, C257S528000, C257S544000

Reexamination Certificate

active

07541652

ABSTRACT:
An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.

REFERENCES:
patent: 2001/0038138 (2001-11-01), Miles et al.
patent: 2002/0164851 (2002-11-01), Wu et al.
Aragones, Xavier et al., “Analysis ans Solutions for Switching Noise Coupling in Mixed-Signal ICs”, Chapter 2, pp. 10-11, 20-25, 36-47 and Chapter 4 pp. 70-86, Kluwer Academic Publishers, Springer; 1st edition (Apr. 30, 1999).
U.S. Appl. No. 10/683,944, filed Oct. 10, 2003, Young.
Charbon, Edoardo et al., “Substrate Noise Analysis and Optimization for IC Design,” 2001, Chapter 8, pp. 99-133, available from Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061.
Aragones, Xavier et al., entitled “Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs”, Chapter 2, pp. 10-11, 20-25, 36-47 and Chapter 4 pp. 70-86, Kluwer Academic Publishers, Springer; 1st edition (Apr. 30, 1999) ISBN-10: 0792385047, ISBN-13: 978-0792385042.

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