MOS transistors having low-resistance salicide gates and a...

Details MOS transistors having low-resistance salicide gates and a... MOS transistors having low-resistance salicide gates and a...

2005-01-24

2009-10-20

Blum, David S (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S382000, C257S412000, C257S758000, C257SE21576

Reexamination Certificate

active

07605414

ABSTRACT:
A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.

REFERENCES:
patent: 6803318 (2004-10-01), Qiao et al.
patent: 6856019 (2005-02-01), Tamaru et al.
patent: 2004/0115874 (2004-06-01), Amon et al.
patent: 1440070 (2003-09-01), None

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