Method for forming vias in a substrate

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S667000, C438S672000, C257SE21575, C257SE21585

Reexamination Certificate

active

07625818

ABSTRACT:
The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform.

REFERENCES:
patent: 5308443 (1994-05-01), Sugihara
patent: 5998292 (1999-12-01), Black et al.
patent: 7222420 (2007-05-01), Moriizumi
patent: 7276787 (2007-10-01), Edelstein et al.
patent: 2004/0259292 (2004-12-01), Beyne et al.
patent: 2007/0048896 (2007-03-01), Andrey et al.

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