Semiconductor memory device realizing high speed access and low

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

3652257, 365194, 36523006, 36523008, G11C 700, G11C 800

Patent

active

057989745

ABSTRACT:
If a row (column) redundant circuit is not used, a comparison between a defective address and an internal address is not performed in a row (column) fuse programming portion in accordance with a signal output from a circuit for indicating if a row (column) redundant circuit is to be used or not. A comparison outcome signal which is generated when these addresses do not match each other is to be output from the row (column) fuse programming portion.

REFERENCES:
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 4905192 (1990-02-01), Nogami et al.
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5343429 (1994-08-01), Nakayama et al.
patent: 5383156 (1995-01-01), Komatsu

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