Out of order DRAM sequencer

Details Out of order DRAM sequencer Out of order DRAM sequencer

2006-11-28

2009-11-17

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S169000, C711S154000, C711S104000, C711S105000

Reexamination Certificate

active

07620789

ABSTRACT:
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requesters in the order in which the read requests were originally received.

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