Structure and method to form improved isolation in a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S506000, C257SE21067

Reexamination Certificate

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07635899

ABSTRACT:
A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

REFERENCES:
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patent: 6818528 (2004-11-01), Mandelman et al.
patent: 6875697 (2005-04-01), Trivedi
patent: 7067387 (2006-06-01), Lin
patent: 2005/0067294 (2005-03-01), Choe et al.
V. Lehmann et al., “Porous Silicon Formation: A Quantum Wire Effect”, Appl. Phys. Lett., vol. 58, No. 8, Feb. 25, 1991, pp. 856-858.

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