Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-10-27
2009-12-08
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S103000
Reexamination Certificate
active
07631162
ABSTRACT:
A memory system is presented where sectors are normally stored in logically contiguous groups. As repeated writes of the same small sector group can causes a massive garbage collection (data relocation), the pattern of host access is monitored by checking the sectors' update history and control data structures' update history. When repeated access patterns are detected and then expected again, the “hot” segments are separated into specially handled, non-standard zone in the memory. The non-standard zone has a sector management that is different from the logical groups and optimized for the repeated host accesses in order to reduce the frequency and amount of garbage collection operations.
REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5274646 (1993-12-01), Brey et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5367484 (1994-11-01), Alexander et al.
patent: 5404485 (1995-04-01), Ban
patent: 5428621 (1995-06-01), Mehrotra et al.
patent: 5465235 (1995-11-01), Miyamoto
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5572466 (1996-11-01), Sukegawa
patent: 5661053 (1997-08-01), Yuan
patent: 5734816 (1998-03-01), Niijima et al.
patent: 5742934 (1998-04-01), Shinohara
patent: 5751634 (1998-05-01), Itoh
patent: 5768192 (1998-06-01), Eitan
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5798968 (1998-08-01), Lee et al.
patent: 5822245 (1998-10-01), Gupta et al.
patent: 5845313 (1998-12-01), Estakhri et al.
patent: 5860124 (1999-01-01), Matthews et al.
patent: 5890192 (1999-03-01), Lee et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 5907856 (1999-05-01), Estakhri et al.
patent: 5909449 (1999-06-01), So et al.
patent: 5930167 (1999-07-01), Lee et al.
patent: 5937425 (1999-08-01), Ban
patent: 6011725 (2000-01-01), Eitan
patent: 6021463 (2000-02-01), Belser
patent: 6034897 (2000-03-01), Estakhri et al.
patent: 6040997 (2000-03-01), Estakhri
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6125435 (2000-09-01), Estakhri et al.
patent: 6141249 (2000-10-01), Estakhri et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6266273 (2001-07-01), Conley et al.
patent: 6272610 (2001-08-01), Katayama et al.
patent: 6282624 (2001-08-01), Kimura et al.
patent: 6317371 (2001-11-01), Katayama et al.
patent: 6374337 (2002-04-01), Estakhri
patent: 6377500 (2002-04-01), Fujimoto et al.
patent: 6388920 (2002-05-01), Katayama et al.
patent: 6421279 (2002-07-01), Tobita et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6449625 (2002-09-01), Wang
patent: 6456528 (2002-09-01), Chen
patent: 6490649 (2002-12-01), Sinclair
patent: 6522580 (2003-02-01), Chen et al.
patent: 6522586 (2003-02-01), Wong
patent: 6525952 (2003-02-01), Araki et al.
patent: 6563734 (2003-05-01), Taki
patent: 6567307 (2003-05-01), Estakhri
patent: 6574705 (2003-06-01), Peloquin et al.
patent: 6581132 (2003-06-01), Kakinuma et al.
patent: 6581142 (2003-06-01), Jacobs
patent: 6591329 (2003-07-01), Kakinuma et al.
patent: 6591330 (2003-07-01), Lasser
patent: 6725321 (2004-04-01), Sinclair et al.
patent: 6763424 (2004-07-01), Conley
patent: 6895464 (2005-05-01), Chow et al.
patent: 6898662 (2005-05-01), Gorobets
patent: 2002/0099904 (2002-07-01), Conley
patent: 2003/0053334 (2003-03-01), Chen
patent: 2003/0065899 (2003-04-01), Gorobets
patent: 2003/0070036 (2003-04-01), Gorobets
patent: 2003/0099134 (2003-05-01), Lasser et al.
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2003/0110343 (2003-06-01), Hagiwara et al.
patent: 2003/0202377 (2003-10-01), Harari et al.
patent: 2003/0227804 (2003-12-01), Lofgren et al.
patent: 2004/0111553 (2004-06-01), Conley
patent: 2005/0073884 (2005-04-01), Gonzalez et al.
patent: 2005/0141312 (2005-06-01), Sinclair et al.
patent: 2005/0141313 (2005-06-01), Gorobets et al.
patent: 2005/0144360 (2005-06-01), Bennett et al.
patent: 2005/0144363 (2005-06-01), Sinclair
patent: 2005/0144365 (2005-06-01), Gorobets et al.
patent: 2005/0166087 (2005-07-01), Gorobets
patent: 0 757 317 (1997-02-01), None
patent: 887732 (1998-12-01), None
patent: 0977121 (2000-02-01), None
patent: 1424631 (2004-06-01), None
patent: 1 548 599 (2005-06-01), None
patent: 5282883 (1993-10-01), None
patent: 5314019 (1993-11-01), None
patent: 11003290 (1999-11-01), None
patent: WO 00/49488 (2000-08-01), None
patent: WO 00/67137 (2000-11-01), None
patent: WO 02/49039 (2002-06-01), None
patent: WO 02/058074 (2002-07-01), None
patent: WO 03/027828 (2003-04-01), None
patent: WO 03/029951 (2003-04-01), None
patent: WO 03/069627 (2003-08-01), None
patent: 2004/040457 (2004-05-01), None
patent: 2004/040458 (2004-05-01), None
patent: 2004/040459 (2004-05-01), None
patent: 2004/040578 (2004-05-01), None
Nakamura et al., “A Novel Sense. Amplifier. for Flexible Voltage Operation NAND Flash Memories,” 1995Symposium on VLSI Circuits Digest of Technical Papers, Jun. 8-10, 1995, pp. 71-72.
Srisa-an et al., “Performance Enhancements to the Active Memory System,”2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sep. 16-18, 2002, pp. 249- 256.
Lee et al., “High-Performance 1-Gb NAND Flash Memory.with 0.12-μm Technology,”Journal of Solid-State Circuits, Nov. 2002, vol. 37, No. 11, pp. 1502-1509.
Imamiya et al., “A 125-mm21-Gb NAND Flash Memory with 10/Mbyte/s Program Speed,”IEEE Journal of Solid State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1493-1501.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell;” IEE Electron Device Letters, vol. 21, No. 1, Nov. 2000,. pp. 543-545.
Chang, Li-Pin et al., “An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems”, Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium, Sep. 24, 2002, pp. 187-196.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the Internation Searching Authority, or the Declaration,” mailed in related International Patent Apllication No. PCT/US2007/060080 on Aug. 17, 2007, 12 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/261,138 on Sep. 21, 2007, 12 pages.
Office Action for U.S. Appl. No. 11/261,138, filed Jul. 2, 2008, 15 pages.
Cardwell Eric S
Davis , Wright, Tremaine, LLP
SanDisck Corporation
Verbrugge Kevin
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