Multiprocessor system and method ensuring coherency between...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S118000, C711S119000, C711S128000, C711S141000, C711S145000, C711S146000, C711S147000, C711S153000

Reexamination Certificate

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07613884

ABSTRACT:
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a copy of a part of a memory region group of the main memory of one node. The memory region group includes memory regions having the same memory address portion including a cache index portion. Each node is assigned one of the directory bits. When accessing the main memory, the node checks whether the directory bits of the directory entry corresponding to a memory region to be accessed are set to a predetermined value, and if one or more of the directory bits of the directory entry are set to the predetermined value, an access address is multicast or broadcast to other nodes to perform coherency control.

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patent: 10240707 (1998-09-01), None
“Stanford Flash Multiprocessor”, Proceedings of the 21st Annual International Symposium onComputer Architecture (Special Issue ISCA′ 21 Proceedings, Apr. 18-21, 1994, p. 302-313.

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