Method and apparatus for designing a PLL

Details Method and apparatus for designing a PLL Method and apparatus for designing a PLL

2006-03-31

2009-11-03

Tran, Khanh C (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07613268

ABSTRACT:
A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.

REFERENCES:
patent: 6914489 (2005-07-01), Charlon
patent: 6993106 (2006-01-01), Momtaz
patent: 7346133 (2008-03-01), Tatem, Jr.
patent: 7420426 (2008-09-01), Herrin et al.
patent: 2002/0191728 (2002-12-01), Hafez et al.
International Search Report dated Aug. 21, 2006, from corresponding PCT patent application No. PCT/CA2006/000639.
Abramovitch, “Analysis and Design of a Third Order Phase-Lock Loop” 1988 IEEE pp. 0455-0459.

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