Methods of forming a metal line in a semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257SE21577, C257SE21586

Reexamination Certificate

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07485574

ABSTRACT:
Methods of forming a metal line in a semiconductor device. A method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; forming a contact hole by etching an exposed portion of the interlayer insulating layer using the contact hole pattern as a mask; forming a trench pattern on the line insulating layer; forming a trench by etching an exposed portion of the line insulating layer using the trench pattern as a mask; removing exposed portions of the first etch stop layer and the second etch stop layer after forming the contact hole and the trench; forming a first metal thin film within the contact hole; and forming a second metal thin film on the first metal thin film.

REFERENCES:
patent: 6258683 (2001-07-01), Besser et al.
patent: 2002/0048949 (2002-04-01), Pyo
patent: 2002/0061645 (2002-05-01), Trivedi et al.
patent: 2003/0134510 (2003-07-01), Lee et al.
patent: 2005/0032368 (2005-02-01), Li et al.
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patent: 2001-168188 (2001-06-01), None
“Electrochemical Planarization by Selective Electroplating for Embedded Gold Wiring in the Sub-Micron Range” 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, Nov. 6-10, 1995, pp. 287-290.
Keji Miyata; Manufacturing Method of Semiconductor Device; Patent Abstracts of Japan; Publication No. 2001-168188; Publication Date: Jun. 22, 2001; Japan Patent Office, Japan.

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