Methods and apparatus to implement parallel transactions

Details Methods and apparatus to implement parallel transactions Methods and apparatus to implement parallel transactions

2006-07-18

2009-02-24

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

Reexamination Certificate

active

07496716

ABSTRACT:
Cache logic associated with a respective one of multiple processing threads executing in parallel updates corresponding data fields of a cache to uniquely mark its contents. The marked contents represent a respective read set for a transaction. For example, at an outset of executing a transaction, a respective processing thread chooses a data value to mark contents of the cache used for producing a transaction outcome for the processing thread. Upon each read of shared data from main memory, the cache stores a copy of the data and marks it as being used during execution of the processing thread. If uniquely marked contents of a respective cache line happen to be displaced (e.g., overwritten) during execution of a processing thread, then the transaction is aborted (rather than being committed to main memory) because there is a possibility that another transaction overwrote a shared data value used during the respective transaction.

REFERENCES:
patent: 2005/0038961 (2005-02-01), Chen
patent: 2007/0124546 (2007-05-01), Blanchard et al.
Chris Purcell et al., Brief Announcement; Implementing Multi-Word Atomic Snapshots on Current Hardware, Jul. 25-28, 2004, p. 1, PODC '04.

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