Semiconductor device capable of avoiding latchup breakdown...

Details Semiconductor device capable of avoiding latchup breakdown... Semiconductor device capable of avoiding latchup breakdown...

2008-06-30

2009-06-09

Doan, Theresa T (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S355000

Reexamination Certificate

active

07545005

ABSTRACT:
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

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U.S. Appl. No. 12/164,739, filed Jun. 30, 2008, Hatade et al.
U.S. Appl. No. 12/164,696, filed Jun. 30, 2008, Hatade et al.

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