Memory control device and move-in buffer control method

Details Memory control device and move-in buffer control method Memory control device and move-in buffer control method

2004-11-19

2009-02-03

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S144000, C711S145000

Reexamination Certificate

active

07487295

ABSTRACT:
A central processor requests for reference to data stored in a main storage for each of a plurality of threads. A thread identification information obtaining unit obtains thread identification information that identifies the threads. A valid MIB detector detects the number of the primary cache MIBs that hold requests of the cache for reference to data stored in the mains storage, for each thread based on the thread identification information. The MIB controller controls to hold reference requests in the primary cache MIBs such that the number of the primary cache MIBs detected for each thread does not exceed a predetermined number.

REFERENCES:
patent: 5023776 (1991-06-01), Gregor
patent: 2001/0032307 (2001-10-01), Rohlman et al.
patent: 2002-342163 (2002-11-01), None
patent: WO 99/27452 (1999-06-01), None
European Search Report, mailed Nov. 7, 2007 and issued in corresponding European Patent Application No. 04257387.3-1229.

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