Method of improving the planarizaton of an inter-metal dielectri

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438627, 438631, 438636, 438637, 438645, 438672, 438675, H01L 214763

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active

059131420

ABSTRACT:
A method of planarizing an inter-metal dielectric layer includes providing a semiconductor substrate having a component layer formed thereon; and forming a metallic layer over the component layer. Then, portions of the metallic layer are etched to form metal pads on the metallic layer surface. Next, the metallic layer is patterned and portions of the metallic layer are etched to form a plurality of metal lines and trenches between the metal lines. Subsequently, a first oxide layer is deposited over the metal lines and the trenches, and then a spin on glass layer is formed over the first oxide layer, filling up the trenches. Thereafter, portions of the spin on glass layer are etched back to expose the metal pad and form a residual spin on glass layer, and then a second oxide layer is formed over the metal pad, the residual spin on glass layer and the first oxide layer. Portions of the second oxide layer are etched to form an opening in the second oxide layer that corresponds to the metal pad location. The opening is subsequently used to form a via plug.

REFERENCES:
patent: 5563099 (1996-10-01), Grass
patent: 5747382 (1998-05-01), Huang et al.
patent: 5789315 (1998-08-01), Besser et al.
patent: 5854503 (1998-11-01), Hsuch et al.

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