Method for forming planar field effect transistors with source a

Details Method for forming planar field effect transistors with source a Method for forming planar field effect transistors with source a

1997-12-12

1999-06-15

Niebling, John F.

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

438969, H01L 2120

Patent

active

059131357

ABSTRACT:
A method for forming a transistor (50) includes forming a first insulating region (16) in the outer surface of a semiconductor body (10) and forming a second insulating region (16) in the outer surface of the semiconductor body (10) and spaced apart from the first insulating region by a region of semiconductor material. The method further includes planarizing the first and second insulating regions and the region of semiconductor material to define a planar surface (17) and forming a conductive source region (34) overlying the first insulating region. The method further includes forming a conductive drain region (36) overlying the second insulating region and forming a conductive gate body (24) overlying the planar surface (17) and spaced apart from the conductive source region (34) and the conductive drain region (36).
A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed in the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).

REFERENCES:
patent: 5110757 (1992-05-01), Arst et al.
patent: 5449642 (1995-09-01), Tan et al.
IEDM 1985, "A Novel MOS Device Structure With S/D Contacts Over Oxide (C00)", pp. 204-207 (C.H. Dennison, A.T. Wu. P.K. Ko, C.J. Drowley and D. Bradbury). Month Unknown.
1996 Symposium on VLSI Technology Digest of Technical Papers, "0.15.mu.m Delta-Doped CMOS With On-Field Source/Drain Contacts", pp. 172-173 (K. Imai, C. Hu, T. Andoh, Y. Kinoshita, Y. Matsubara, T. Tatsumi and Yamazaki) Month Unknown.

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