Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Common read and write circuit

Reexamination Certificate

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Details

C365S189160, C365S154000, C365S230060

Reexamination Certificate

active

07599232

ABSTRACT:
A word line driving circuit includes first, second, and third MOS transistors. Gates of the first and second transistors are commonly connected. Sources of the first and second transistors are connected to different power supplies. The third transistor is connected between the drains of the first and second transistors. A connection node between the drains of the second and third transistors is connected to a word line. When the input signal is set to a high level and the second transistor is turned on, a potential lower than a high level of the input signal is supplied to a gate of the third MOS transistor. A signal with a high level thereof being lower than a high level of the input signal, or a fixed GND potential is supplied to the gate of the third transistor.

REFERENCES:
patent: 5513147 (1996-04-01), Prickett, Jr.
patent: 5808956 (1998-09-01), Maruyama
patent: 6084804 (2000-07-01), McPartland
patent: 6339344 (2002-01-01), Sakata et al.
patent: 7184358 (2007-02-01), Kobayashi et al.
patent: 2000-306382 (2000-11-01), None
patent: 2005-158223 (2005-06-01), None
patent: 2005-192234 (2005-07-01), None

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