Semiconductor transistor having a stressed channel

Details Semiconductor transistor having a stressed channel Semiconductor transistor having a stressed channel

2005-09-09

2009-02-17

Ngo, Ngan (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S192000, C257S194000, C257S116000, C257SE29121, C257SE29122, C257SE29193, C438S413000

Reexamination Certificate

active

07492017

ABSTRACT:
A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSATand IDLINof the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

REFERENCES:
patent: 4633099 (1986-12-01), Tanabe et al.
patent: 4952993 (1990-08-01), Okumura
patent: 5683934 (1997-11-01), Candelaria
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5763319 (1998-06-01), Ling et al.
patent: 5841173 (1998-11-01), Yamashita
patent: 5956590 (1999-09-01), Hsieh et al.
patent: 5970329 (1999-10-01), Cha
patent: 5990516 (1999-11-01), Momose et al.
patent: 5994747 (1999-11-01), Wu
patent: 6110786 (2000-08-01), Gardner et al.
patent: 6190975 (2001-02-01), Kubo et al.
patent: 6380088 (2002-04-01), Chan
patent: 6391703 (2002-05-01), Rovedo et al.
patent: 6403482 (2002-06-01), Rovedo et al.
patent: 6437404 (2002-08-01), Xiang et al.
patent: 6544874 (2003-04-01), Mandelman et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
Ng, Kwok K., “Complete Guide to Semiconductor Device,” McGraw-Hill, p. 614.
Ouyang, Q., et al., “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFET with Enhanced Device Performance and Scalability,” IEEE 2000, 0-7803-6279-9/00, pp. 151-154.
Ozturk .M.C., et al., “Ultra-Shallow Source/Drain Junctions for Nanoscale CMOS Using Selective Silicon-Germanium Technology,” Extended Abstracts of International Workshop on Junction Technology 2001, Japan Society of Applied Physics. ISBN 4-89114-019-4/020-8, pp. 5-1-1 to 5-1-6.
Steegen, An et al., “Silicide Induced Pattern Density and Orientation Dependent Transconductance in MOS Transistors,” IEEE 1999, IMEC, Belgium and INSYS, IEDM 99-497, pp. 20.1.1-20.1.4.

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