Semiconductor memory device and semiconductor device...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21662, C257SE21680

Reexamination Certificate

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07541654

ABSTRACT:
In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.

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U.S. Appl. No. 11/980,561, filed Oct. 31, 2007, Sakuma, et al.
U.S. Appl. No. 12/143,597, filed Jun. 20, 2008, Sakuma, et al.

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