Method and apparatus for implementing balanced clock...

Details Method and apparatus for implementing balanced clock... Method and apparatus for implementing balanced clock...

2008-01-15

2009-06-23

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S038000, C326S040000

Reexamination Certificate

active

07551002

ABSTRACT:
A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

REFERENCES:
patent: 6081145 (2000-06-01), Bandai et al.
patent: 6429715 (2002-08-01), Bapat et al.
patent: 6856171 (2005-02-01), Zhang
patent: 6879202 (2005-04-01), Nguyen
patent: 2003/0197529 (2003-10-01), Campbell
patent: 2008/0303552 (2008-12-01), Chueh et al.

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