Semiconductor device improving error correction processing rate

Details Semiconductor device improving error correction processing rate Semiconductor device improving error correction processing rate

2005-06-09

2009-06-23

Baker, Stephen M (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C365S200000, C714S801000

Reexamination Certificate

active

07552378

ABSTRACT:
In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

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Masaaki Mitani, “Industrial Mathematics for Restudy,” Jan. 1, 2001, CQ Publishing Co., Ltd., pp. 47-53 (Translation Provided).

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