Semiconductor memory devices with charge traps

Details Semiconductor memory devices with charge traps Semiconductor memory devices with charge traps

2007-09-05

2009-10-13

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29309, C257SE21423, C257S640000, C438S216000

Reexamination Certificate

active

07602012

ABSTRACT:
A memory cell in a semiconductor memory device has a pair of charge traps formed on opposite sides of a control electrode, above variable resistance regions in the semiconductor substrate. Each charge trap includes a tunnel oxide film, a dual-layer charge trapping film, and a top oxide film. The dual-layer charge trapping film includes a silicon-rich silicon nitride layer or amorphous silicon layer adjacent to the tunnel oxide film, and a stoichiometric or nitrogen-rich silicon nitride layer adjacent to the top oxide film. Most charges injected into the charge trapping film are trapped in the layer adjacent to the tunnel oxide film, near the substrate, which facilitates the reading of the data that the trapped charges represent.

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