Method and device for designing semiconductor integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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07624361

ABSTRACT:
A method and device for designing a semiconductor integrated circuit that easily reduces off leakage current. Wires connected to input terminals of a standard cell are exchanged with one another and a gate net list is changed so as to reduce off leakage current in accordance with a net probability and a current consumption table. The net probability is the probability of the state an input of the standard cell can take and is generated through an RTL function simulation and a gate level function simulation. The current consumption table is stored in a technology library storage.

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patent: 2005190237 (2005-07-01), None

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