Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-08-03
2009-02-24
Smith, Matthew (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S160000, C438S443000, C438S458000, C438S459000, C257S117000, C257S118000, C257S276000, C257S502000, C257S678000
Reexamination Certificate
active
07494909
ABSTRACT:
Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.
REFERENCES:
patent: 6261943 (2001-07-01), Grupp
patent: 6395630 (2002-05-01), Ahn et al.
patent: 6485814 (2002-11-01), Moriizumi et al.
patent: 6916725 (2005-07-01), Yamaguchi
patent: 7119001 (2006-10-01), Kang
patent: 7399683 (2008-07-01), Noma et al.
patent: 2003/0134453 (2003-07-01), Prabhu et al.
patent: 2005/0017358 (2005-01-01), Farnworth
patent: 2005/0110157 (2005-05-01), Sherrer et al.
patent: 2005/0215054 (2005-09-01), Rasmussen et al.
patent: 2005/0224966 (2005-10-01), Fogel et al.
patent: 2006/0040451 (2006-02-01), Lotfi et al.
patent: 2006/0043535 (2006-03-01), Hiatt
patent: 2006/0223340 (2006-10-01), Yoneda
patent: 2007/0001266 (2007-01-01), Arana et al.
patent: 2007/0045780 (2007-03-01), Akram et al.
patent: 2002-0012061 (2002-02-01), None
patent: 10-2005-0021078 (2005-03-01), None
“Development of Advanced 3D Chip Stacking Technology with Ultra-Fine Interconnection,” by Kenji Takahashi et al.;IEEE Electronic Components and Technology Conference; 2001.
Ju Chull Won
Kang Young Il
Kim Seong Il
Lee Jong Min
Lee Kyung Ho
Blakely , Sokoloff, Taylor & Zafman LLP
Electronics and Telecommunications Research Institute
Mitchell James M
Smith Matthew
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