Wafer stacked package having vertical heat emission path and...

Details Wafer stacked package having vertical heat emission path and... Wafer stacked package having vertical heat emission path and...

2007-10-29

2009-12-01

Sefer, A. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S715000, C257SE23082, C257SE23080, C257SE23102, C257SE31131

Reexamination Certificate

active

07626261

ABSTRACT:
A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

REFERENCES:
patent: 6236568 (2001-05-01), Lai et al.
patent: 6251707 (2001-06-01), Bernier et al.
patent: 2003/0131968 (2003-07-01), Chrysler et al.
patent: 2006/0197181 (2006-09-01), Noguchi
patent: 2001-156247 (2001-06-01), None
patent: 2001-168255 (2001-06-01), None
patent: 2000022292 (2000-04-01), None
English language abstract of Japanese Publication No. 2001-156247.
English language abstract of Japanese Publication No. 2001-168255.

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