Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-11-29

2009-12-08

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S201000

Reexamination Certificate

active

07630229

ABSTRACT:
A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal. A first power supply voltage is applied to the first power supply terminal. A ground voltage is applied to the second power supply terminal. A source voltage higher than the ground voltage is applied to the third power supply terminal.

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patent: 2004-5777 (2004-01-01), None
Y. Takeyama et al., “A Low Leakage SRAM Macro with Replica Cell Biasing Scheme”, VLSI Circuits 2005, 2 pages.
Kyeong-Sik Min et al., “Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDDSRAM's”, Low Power Electronics and Design, 2003 ISLPLED. Proceedings of the 2003 International Symposium on Aug. 25-27, 2003, pp. 66-71.
Y. Takeyama et al., “A Low Leakage SRAM Macro with Replica Cell Biasing Scheme”, VLSI Circuits 2005, 2 pages.

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