Sub-lithographic nano interconnect structures, and method...

Details Sub-lithographic nano interconnect structures, and method... Sub-lithographic nano interconnect structures, and method...

2006-10-19

2009-06-30

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S702000, C438S736000, C257SE21575

Reexamination Certificate

active

07553760

ABSTRACT:
A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

REFERENCES:
patent: 2004/0127001 (2004-07-01), Colburn et al.
Nealey et al., “Self-Assembling Resists for Nanolithography,” IEEE, 2005.
Guarini et al., “Nanoscale patterning Using Self-Assembled Polymers for Semiconductor Applications,” J. Vac. Sci. Technol., Nov./Dec. 2001, pp. 2784-2788, B 19(6).

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